Systems and methods for linear variable gain amplifier

ABSTRACT

The present invention is directed to electrical circuits. In a specific embodiment, the present invention provides variable gain amplifier that includes an impedance ladder and a control circuit. The impedance ladder includes n switches configured in parallel. The control circuit includes a digital-to-analog converter and an amplifier. The control circuit generates n control signals for the n switches. There are other embodiments as well.

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BACKGROUND OF THE INVENTION

The present invention is directed to electrical circuits and techniquesthereof.

A variable gain amplifier (VGA) has many applications. Typically, avariable-gain or voltage-controlled amplifier is an electronic amplifierthat varies its gain depending on a control voltage (CV)/digital controlword. VGAs have many applications, including audio level compression,synthesizers, amplitude modulation, and others. For example, a VGA canbe implemented by first creating a voltage-controlled resistor (VCR),which is used to set the amplifier gain. The VCR can be produced by oneor more transistors with simple biasing. In certain implementations,VGAs are implemented using operational trans-conductance amplifiers(OTA). Sometimes, VGAs are implemented for automatic gain control (AGC)applications. Typically, VGA performance can be measured in terms ofgain range, the linearity of electrical characteristics, distortion,tunability, and bandwidth.

Over the past, many types of conventional variable gain amplifiers havebeen proposed and implemented in different applications. Unfortunately,existing variable gain amplifiers are inadequate, as explained below. Itis thus desirable to have new and improved variable gain amplifiers.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to electrical circuits. In a specificembodiment, the present invention provides a variable gain amplifierthat includes an impedance ladder and a control circuit. The impedanceladder includes n switches configured in parallel. The control circuitincludes a digital-to-analog converter and an amplifier. The controlcircuit generates n control signals for the n switches. There are otherembodiments as well.

According to an embodiment, the present invention provides a variablegain amplifier device that includes a first input switch coupled to afirst differential input. The device also includes a second input switchcoupled to a second differential input. The device also includes adegeneration resistor coupled to the first input switch and the secondinput switch. The device also includes an impedance ladder circuitconfigured in parallel with the degeneration resistor. The impedanceladder circuit may include n switches. The n switches may be configuredwith a predetermined scale. The device also includes a control circuitconfigured to generate n control signals for the n switches. The controlcircuit may include a digital-to-analog converter (DAC) and anoperational transconductance amplifier (OTA) and a plurality ofreference resistors. The OTA may be configured in a feedback loop.

According to another embodiment, the present invention provides areceiver device that includes an input terminal for receiving an inputsignal. The device also includes a termination circuit for adjusting theinput signal. The device also includes an equalizer configured toequalize the input signal and generate an equalized signal. The devicealso includes a variable gain amplifier (VGA) configured to adjust theequalized signal by a gain factor. The VGA may include adjustableimpedance. The adjustable impedance may include an impedance ladder anda control circuit. The impedance ladder may include n switches. Thecontrol circuit may include a digital-to-analog converter (DAC) and anamplifier. The control circuit is configured to generate n controlsignals for the n switches. The amplifier is configured in a feedbackloop.

According to yet another embodiment, the present invention provides avariable gain amplifier device that is characterized by a gain factor.The variable gain amplifier device includes an impedance ladder circuitcharacterized by an impedance value. The impedance value is associatedwith the gain factor. The impedance ladder circuit may include nswitches. The n switches are configured with a predetermined scale. Thedevice also includes a digital-to-analog converter (DAC) configured toconvert a control code to a DAC signal. The device also includes anoperational transconductance amplifier (OTA) that may include a firstinput and a second input and an output. The first input is coupled tothe DAC signal. The second input is coupled to the output. The devicealso includes a plurality of reference resistors coupled to the output.The device also includes a current source coupled to the plurality ofreference resistors. The device also includes n control terminalscoupled to the n switches and the plurality of reference resistors.

It is to be appreciated that embodiments of the present inventionprovide many advantages over conventional techniques. Compared toconventional techniques, VGA architecture according to embodiments ofthe present invention can provide a high level of linearity andtunability.

Embodiments of the present invention can be implemented in conjunctionwith existing systems and processes. For example, existing communicationdevices such as SerDes can readily incorporate embodiments of thepresent invention. VGA architectures according to embodiments of thepresent invention can take advantage of front end CTLE configurationsthat are already parts of communication devices. Embodiments of thepresent invention are compatible with existing manufacturing processesand equipment. There are other benefits as well.

The present invention achieves these benefits and others in the contextof known technology. However, a further understanding of the nature andadvantages of the present invention may be realized by reference to thelatter portions of the specification and attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The following diagrams are merely examples, which should not undulylimit the scope of the claims herein. One of ordinary skill in the artwould recognize many other variations, modifications, and alternatives.It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this process andscope of the appended claims.

FIG. 1A is a simplified block diagram illustrating a communicationsystem according to embodiments of the present invention.

FIG. 1B is a simplified diagram of a VGA 150 according to embodiments ofthe present invention.

FIG. 2 is a simplified diagram of a VGA according to embodiments of thepresent invention.

FIG. 3 is a simplified diagram of a VGA showing a bias loop and afeedback loop according to embodiments of the present invention.

FIG. 4 is a simplified diagram illustrating a control circuit accordingto embodiments of the present invention.

FIG. 5 is a plot illustrating an exemplary control voltage generationscheme according to embodiments of the present invention.

FIG. 6 provides plots illustrating an exemplary VGA gain relative tocontrol voltage according to embodiments of the present invention.

FIG. 7 is a simplified diagram illustrating an OTA 700 according toembodiments of the present invention.

FIG. 8 is a simplified diagram illustrating an impedance ladderaccording to embodiments of the present invention.

FIG. 9 is a simplified diagram illustrating degeneration resistancevalue relative to control voltage according to embodiments of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to electrical circuits. In a specificembodiment, the present invention provides a variable gain amplifierthat includes an impedance ladder and a control circuit. The impedanceladder includes n switches configured in parallel. The control circuitincludes a digital-to-analog converter and an amplifier. The controlcircuit generates n control signals for the n switches. There are otherembodiments as well.

Various embodiments of the present invention afford linearization ofvariable gain amplifiers (VGA), which can be used for high-speedwireline communication link receivers. Exemplary VGAs, as describedbelow, eliminate the need for a high-resolution digital-to-analogconverter (DAC) for gain calibration by using a control circuit (e.g., aramp circuit) based on an operational transconductance amplifier (OTA).For example, an exemplary ramp circuit includes an OTA and amedium-resolution DAC. An exponential scaling of the degeneration metaloxide semiconductor (MOS) devices is used to provide good linearity andsmall gain steps during VGA calibration (when used in conjunction withramp circuits). It is to be appreciated that exponential scaling ofdegeneration device—implemented without the need resistors configured inseries—allows for the optimum area, speed, and linearity.

The following description is presented to enable one of ordinary skillin the art to make and use the invention and to incorporate it in thecontext of particular applications. Various modifications, as well as avariety of uses in different applications will be readily apparent tothose skilled in the art, and the general principles defined herein maybe applied to a wide range of embodiments. Thus, the present inventionis not intended to be limited to the embodiments presented, but is to beaccorded the widest scope consistent with the principles and novelfeatures disclosed herein.

In the following detailed description, numerous specific details are setforth in order to provide a more thorough understanding of the presentinvention. However, it will be apparent to one skilled in the art thatthe present invention may be practiced without necessarily being limitedto these specific details. In other instances, well-known structures anddevices are shown in block diagram form, rather than in detail, in orderto avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which arefiled concurrently with this specification and which are open to publicinspection with this specification, and the contents of all such papersand documents are incorporated herein by reference. All the featuresdisclosed in this specification, (including any accompanying claims,abstract, and drawings) may be replaced by alternative features servingthe same, equivalent or similar purpose, unless expressly statedotherwise. Thus, unless expressly stated otherwise, each featuredisclosed is one example only of a generic series of equivalent orsimilar features.

Furthermore, any element in a claim that does not explicitly state“means for” performing a specified function, or “step for” performing aspecific function, is not to be interpreted as a “means” or “step”clause as specified in 35 U.S.C. Section 112, Paragraph 6. Inparticular, the use of “step of” or “act of” in the Claims herein is notintended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.

Please note, if used, the labels left, right, front, back, top, bottom,forward, reverse, clockwise and counter-clockwise have been used forconvenience purposes only and are not intended to imply any particularfixed direction. Instead, they are used to reflect relative locationsand/or directions between various portions of an object.

As explained above, variable gain amplifiers (VGA) have a wide range ofapplications. For example, VGAs are often used in communicationapplications. For example, as a part of a serializer/deserializer(SerDes) system, a VGA can be used to amplify the amplitude of thereceived analog signal before other processing techniques (e.g., clockrecovery, ADC conversion, etc.) are performed. Depending on the actualapplication and implementation of VGAs, there are various desirable VGAcharacteristics, such as low noise, small parasitic capacitance on theoutput nodes, and high linearity.

It is to be appreciated that according to various embodiments of thepresent invention, VGAs are implemented in conjunction withcontinuous-time linear equalizers. Continuous-time linear equalizers aretypically included in various types of communication and data processingsystems. For example, a SerDes system includes both a transmitter moduleand a receiver module. Received analog signals, transmitted as adifferential pair, are first processed by a continuous-time linearequalizer (CTLE) and then amplified by a VGA. In various embodiments ofthe presentation invention, VGAs are implemented in conjunction withCTLE. Additionally, one or more digital-to-analog converters (DAC) areused to provide control signals for both the CTLE and the VGA.

It is to be appreciated that in a high-speed rate wireline receiver,equalization circuits are used to compensate for the loss of the channeland extend the maximum data rate. For example, an equalization circuitmay be a CTLE and/or an analog implementation of a feed-forwardequalizer (FFE). However, the use of such front-end circuits typicallyresults in a reduction of signal amplitude which must be compensated forso that the final decision circuit has the maximum dynamic range tomitigate its input-referred noise and to ensure sufficiently shortregeneration time to make an error-free decision. This is done using aVGA with enough gain range which can be tuned using some sort ofautomatic gain control (AGC) calibration. For high data rates, the VGAdesign becomes challenging and involves optimizing the performance. Forexample, VGA performance can be measure in terms of large gain range,low power, high linearity with large input/output swing, small gain step(e.g., an order of 0.1-0.2 dB/step), large bandwidth to minimizefrequency-dependent losses and/or settling error, and others. It is tobe appreciated that embodiments of the present invention can achievehigh performance under these metrics, as explained below.

FIG. 1A is a simplified block diagram illustrating a communicationsystem according to embodiments of the present invention. This diagramis merely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. In FIG. 1, the transmitter(TX) transmits a data signal, as a differential signal, to the receiver(RX) via a pair of communication channels. For example, thecommunication channels can be existing copper wires. At the receiver,the input signals are received at the input terminals with inductorcoils and input resistors that improve signal quality. The CTLE moduleis implemented as a part of the receiver. Input signals are equalized bythe CTLE before further processing. For example, loss of signaldetection (LOSD) module determines whether there is a signal beingreceived. Once it is determined that there are signals coming from thetransmitting entity (TX), equalization is performed by the CTLE module.On the other hand, if the LOSD module fails to detect the signalpresence (or detecting a lack of signal presence), signal processing isnot performed. For example, the CTLE module is used as a component of ananalog front end portion of the communication device. The equalizedsignal, which is a differential pair, is then provided to the VGA asshow. The VGA is specifically configured to amplify the received signalby a predetermined amount, and the VGA operates in conjunction withCTLE. For example, compared to conventional VGAs implemented withswitchable resistor array, VGA implementations according to embodimentsof the present invention offer improved performance by taking advantageof the CTLEs. It is to be appreciated that the use of CTLEs with VGAstakes advantage of the fact that CTLEs are essential front end circuitof the receiver devices. For example, receivers are generallyimplemented with CTLEs followed by one or more VGAs. For example, theVGA is configured to enable constant output voltage swing at the outputfor a different set of channel lengths by adjusting the gain controlcode. It is to be appreciated that VGAs according to an embodiment ofthe present invention help maintain linearity. The available signalswing at the output stage can be adjusted using VGAs. For ADC basedcommunication links, automatic gain control often allows for reducedresolution and full-scale range requirement of the ADCs. As mentionedabove, VGAs implemented according to embodiments of the presentinvention utilize OTA and impedance ladder to provide a high degree oftunability and linearity, among other benefits.

As shown in FIG. 1A, after equalization is performed by the CTLE moduleand adjusted by the VGA, signal processing such as clock data recovery(CDR), analog to digital conversion (ADC), and/or other processes arethen performed. It is to be appreciated that the receiver illustrated inFIG. 1 can be used in a variety of applications and systems. Forexample, the receiver can be a part of a transceiver device. In variousembodiments, receivers are implemented as parts of SerDes system.

FIG. 1B is a simplified diagram of a VGA 150 according to embodiments ofthe present invention. This diagram is merely an example, which shouldnot unduly limit the scope of the claims. One of ordinary skill in theart would recognize many variations, alternatives, and modifications. Asan example, VGA 150 is a differentiation amplifier whose gain can beadjusted via degeneration resistor R_(DEG). More specifically, the inputstage consists of a P-type MOS (pMOS) differential pair withdegeneration resistor (R_(DEG)), which may be implemented using anotherpMOS device. This degeneration resistance value can be adjusted usingthe V_(CTRL) voltage which is provided usually by a high-resolution DAC.The load consists of a simple resistor (R_(L)) connected to the ground.Without loss of generality, this VGA can also be implemented using anN-type MOS (nMOS) as well. In a differential implementation, acommon-mode feedback (CMFB) circuit might be needed for the outputcommon mode. In various embodiments, the degeneration resistor R_(DEG)is implemented using an impedance ladder designed according toembodiments of the present invention. As an example, the gain A of VGA150 from the differential input (V_(INP)−V_(INM)) to the differentialoutput (V_(OUTP)−V_(OUTM)) can be written as:

$A = {\frac{V_{OUT}}{V_{IN}} = \frac{2G_{M}R_{L}}{2 + {G_{M}R_{DEG}}}}$where G_(M) is the transconductance of the input device. For small swingacross its source and drain terminals, the R_(DEG) can be represented asa linear resistor of value

$R_{DEG} = \frac{1}{\beta\left( {V_{CM} - V_{CTRL} - {V_{T}}} \right)}$where β is a constant which depends on the size (W/L) and other deviceparameters, V_(CM) is the common-mode voltage at the sources of theinput devices (M_(D)) and V_(T) is the threshold voltage. As is evident,for small values of V_(CTRL), the R_(DEG) reduces, increasing the gainfrom input to output and vice versa.

By design, the G_(M) is kept large for noise and speed reasons. For suchlarge G_(M), the gain for lower gain codes, can be approximated as

$A \approx \frac{2R_{L}}{R_{DEG}}$With a large G_(M) assumption, the source terminals of the inputdifferential pair see the full input differential signal without muchattenuation.

The non-linearity of the VGA usually comes from two sources. Thenon-linearity of input pair G_(M) is a function of the swing across itsV_(GS) and V_(DS) terminals. The non-linearity of the degenerationswitch also contributes to non-linearity, since the resistance realizedwith a MOS switch is inherently non-linear. The non-linearity caused byG_(M) variation can be reduced by keeping the G_(M) large enough and/orusing local loops to suppress V_(DS) variation. It is to be appreciatedthat degeneration resistor R_(DEG) in VGA 150 is replaced by animpedance ladder circuit according to various embodiments, whichimproves the non-linearity caused by the degeneration switch R_(DEG). Asan example, an expression for the degeneration resistance is shownbelow:

$R_{DEG} = \frac{1}{\beta\left( {V_{CM} - V_{CTRL} - {V_{T}} - V_{IN}} \right)}$where V_(IN) is the differential signal across the degeneration switch(same as input differential voltage when the input pair G_(M) is large).Going back to the gain expression,

${A \approx \frac{2R_{L}}{R_{DEG}}} = {2\beta{R_{L}\left( {V_{CM} - V_{CTRL} - {V_{T}} - V_{IN}} \right)}}$

Since the gain itself is a function of V_(IN) instead of being aconstant value, V_(OUT) contains higher harmonics of input frequencywhich explains the non-linear terms in VGA output. Thus, schemes tolinearize the degeneration resistance linearize the transfer functionand improves the non-linearity.

Over the past, there have been various techniques to improve VGAperformance by modifying the degeneration resistor. For example, aregeneration resistor may be implemented with two switches of differentsizes—each with its DAC and control voltage thereof—that provideimproved linearity, but the improvement is limited, due to effectiveparallel resistance issues. As another example, there are VGAimplementations with multiple DACs generating multiple control currentfor multiple switches, but this type of implementation usually resultsin a large area and power penalty.

FIG. 2 is a simplified diagram of a VGA according to embodiments of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications. VGA200 as shown is configured as a differential amplifier, withdifferential inputs (V_(INP) and V_(INM)) and differential outputs(V_(OUTM) and V_(OUTP)). For example, NMOS switches may be used as inputswitches as shown, but other types of switches (e.g., PMOS, BJT, etc.)can be used as input switches coupling to differential inputs as well.Load resistors R_(L) and the common-mode feedback (CMFB) loop arecoupled to the drain terminals of the input switches.

An impedance ladder 220 is configured in parallel to the degenerationresistor R_(DEG), which is coupled to the source terminals of the inputswitches. It is to be understood that the gain of VGA 200 is adjustedvia the impedance ladder 220; other components of VGA 200 may bemodified or otherwise configured depending on the specificimplementation. For example, impedance ladder 220 is configured as adegeneration device consists of five exponentially scaled switches inparallel, which can cover a large gain range with few devices (noresistors). In various embodiments, switches 221-225 are made from unitcells to ensure that the sizing ratio is accurate. The control circuit210 provides control signals that are coupled to the respective switchesat impedance ladder 220. Depending on the implementation, controlcircuit 210 generates n control signals for n switches at impedanceladder 220. As an example, FIG. 5 shows five control signalsV_(CTRL<0-4>) correspond to five switches 221-225. For example, the fivecontrol currents are based on five ramp-generated voltages that are usedto linearize the VGA. It is to be appreciated that the impedance ladder220 does not include resistors that might introduce non-linearity. Atthe control circuit side, the use of an OTA based ramp-gen circuitryimproves the matching between degeneration switch controls andeliminates the need for series resistors in the degeneration switch.Among other benefits, various implementations according to the presentdisclosure provide an area and power-efficient solution for improvingVGA non-linearity and gain step.

FIG. 3 is a simplified diagram of VGA 300 showing a bias loop and afeedback loop according to embodiments of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. For example, VGA 300 isconfigured as a differential amplifier. Among other features, VGA 300includes a replica bias loop 310 as shown. For example, bias loop 310includes an amplifier A₁ that matches amplifier A₂, with V_(OCM) as oneof its inputs. Replica bias loop 310 is configured for generatingoptimum bias current. VGA also includes a CMFB loop for maintaining theright CM voltage at the output.

FIG. 4 is a simplified diagram illustrating a control circuit accordingto embodiments of the present invention. This diagram is merely anexample, which should not unduly limit the scope of the claims. One ofordinary skill in the art would recognize many variations, alternatives,and modifications. Control circuit 400 includes a DAC 401, amplifier402, and output terminals configured with reference resistors R_(REF).In various embodiments, DAC 401 receives a codeword (e.g., from acontroller module) for generating a DAC output signal. For example, thecodeword and the DAC output signal can be pre-calibrated to produce thedesired gain at the VGA. The codeword may be generated by a controlleror obtained from a lookup table (LUT).

The output of DAC 401 is coupled to amplifier 402. In variousimplementations, a filter (e.g., a capacitor) is configured between DAC401 and amplifier 402. Amplifier 402 can be implemented using an OTA.For example, the ramp voltages are generated using a rail-to-rail OTAthat maintains the V_(CTRL<2>) at the same level as the DAC output.Other control signals (i.e., V_(CTRL<1-4>)) are generated by tappinghigher or lower in the resistance ladder, which includes a referencecurrent source I_(REF) and reference resistors R_(REF). As shown on FIG.4, control signals V_(CTRL<1-4>) correspond to different positionsrelative to reference resistors R_(REF). By providing a large gain, OTA402 works as a unity gain buffer for DAC 401 with the minimum errorbetween its input and output. The output voltage V_(FORCE) of the OTAcan be written as

$\frac{V_{FORCE}}{V_{DAC\_ FILT}} = \frac{A_{0}}{1 + A_{0}}$where A₀ is the open-loop gain of the OTA 402. As is evident from theequation, for large values of A₀, the OTA output tracks its input (DACoutput) with negligible error. For example, V_(SENSE) as shown isconfigured as a feedback signal for OTA 402. With the added offsetgeneration branch using I_(REF) & R_(REF), control circuit 400 affords asimple generation of positive and negative offsets from the DAC voltagewithout resorting to multiple current mirrors and offset currents.

In various implementations, OTA 402 only needs to drive the differencein top and bottom current sources, it can be designed with low power.The OTA used in this design is a complementary input stage (nMOS+pMOS)folded cascode opamp with a class AB driver which allows rail to railinput/output operation. The offset of the OTA is not a major concernsince that can be corrected by just adjusting the DAC codes duringcalibration. As can be seen in FIG. 4, only a smaller number of devicesare used, with common offset currents (I_(REF)) and matched polyresistors, control circuit 400 offers great matching between rampvoltage offsets.

Control circuit 400 also provides ramp voltages that are generated on asingle series arm, as compared to parallel arms; its means that toincrease the number of ramp voltages (or output control signals), theresistors (i.e., R_(REF)) can be split up, and taps can be configuredbetween voltages. The design of control circuit 400 allows for efficientand convenient scaling much power penalty. For example, the controlsignals (or offset voltages) can be programmable by adjusting I_(REF) orR_(REF).

It is to be understood that to arrive at the optimum number of rampcontrols needed and the ratio between different degeneration devices, itis important to carefully examine the constraints involved. As anexample, the gain for the VGA when expressed in dB is as follows:A _(dB)=20 log₁₀(2G _(M) R _(L))−20 log₁₀(2+G _(M) R _(DEG))where R_(DEG) is a function of the control voltage V_(CTRL). Since G_(M)& R_(L) are independent of V_(CTRL) and G_(M)R_(DEG) is reasonablylarger than 2, the gain can be expressed as:A _(dB) ≈K−20 log₁₀(R _(DEG))where K is a constant term. Thus, it can be seen that to get a linearA_(dB), R_(DEG) needs to be linear in dB scale, or in other words,R_(DEG) should have an exponential dependence on V_(CTRL) as:R _(DEG) ≈R _(C)10^((mV) ^(CTRL) ^(+b))

In various embodiments, an exponential R_(DEG) is obtained by shiftingthe individual degeneration resistance curves and scaling themexponentially so that the resultant parallel combination mimics anexponential function with minimum error. This is related to theindividual MOS resistance variation (on a logarithmic scale in they-axis) and the equivalent parallel resistance tracking an exponentialresistance.

FIG. 5 is a plot illustrating an exemplary control voltage generationscheme according to embodiments of the present invention. This diagramis merely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. For example, the slope (DACcode vs. control voltage) control signals V_(CTRL<0-4>) may bepredetermined or pre-calibrated corresponding desired degenerationresistance, which translates to desired VGA gain.

FIG. 6 provides plots illustrating an exemplary VGA gain relative tocontrol voltage according to embodiments of the present invention. Thisdiagram is merely an example, which should not unduly limit the scope ofthe claims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. The top plot (showingcontrol voltage vs. gain) shows that the ramp-gen circuit-based VGAsaccording to various embodiments offer a much higher level of linearitycompared to conventional designs. The bottom plot (showing controlvoltage vs. gain slope) provides another way to show that the ramp-gencircuit based VGAs according to various embodiments provides a muchhigher level of linearity (up to 5 times as shown) compared toconventional designs; the improvement in the gain slope is about 5×,which can be directly translated to improvement in gain step. Asexplained above, ramp-generation circuitry according to variousembodiments generates staggered control signals that turn on thedegeneration devices from the lowest to the highest as DAC codeincreases. For each DAC code, the smallest (e.g., “weakest”) devicereceives more gate drive than a bigger (e.g., “stronger”) device thatgenerates a linear resistance (in dB scale) as a function of theequivalent gate voltage.

FIG. 7 is a simplified diagram illustrating an OTA 700 according toembodiments of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. As explained above, an OTA used in a control circuit(e.g., control circuit 400 in FIG. 4) only needs to drive the differencein top and bottom current sources, it can be designed with low power.For example, OTA 700 includes a complementary input stage (nMOS+pMOS)folded cascode opamp with a class AB driver which allows rail-to-railinput/output operation. The offset of the OTA, as used in variousimplementations, is not a major concern since that can be corrected byjust adjusting the DAC codes during calibration. It is to be appreciatedthat due to the presence of a smaller number of devices, common offsetcurrents (e.g., I_(REF) in FIG. 4) and improved matching of polyresistors (e.g., R_(REF)) over MOS, the control circuit (e.g., or rampgeneration circuit) can offer great matching between ramp voltageoffsets.

FIG. 8 is a simplified diagram illustrating an impedance ladderaccording to embodiments of the present invention. This diagram ismerely an example, which should not unduly limit the scope of theclaims. One of ordinary skill in the art would recognize manyvariations, alternatives, and modifications. In various embodiments,impedance ladder 800 includes switches 801-805. It is to be appreciatedthat there is no resistor configured in the impedance ladder 800, andsuch configurations allow for a high level of linearity and efficiency.For example, switches 801-805—acting as variable resistors responsive tocontrol signals—are implemented using MOS devices. In variousembodiments, the number of switches corresponds to the number of controlsignals generated by the control circuits. For example, switches 801-805are manufactured using the same semiconductor die and process, whichallow for a high level of consistency and matching. The ratio among theswitches—1 x, 1.33 x, 4 x, 12 x, 102 x—is based on an exponential scale(i.e., for an exponential curve fit) and calibrated in conjunction withcontrol signals, and it is configured for the convenient adjustment ofthe VGA. Depending on the implementation, the size and number ofswitches can be configured differently.

FIG. 9 is a simplified diagram illustrating degeneration resistancevalue relative to control voltage according to embodiments of thepresent invention. This diagram is merely an example, which should notunduly limit the scope of the claims. One of ordinary skill in the artwould recognize many variations, alternatives, and modifications. Asexplained above, degeneration resistance is associated with theimpedance value of the impedance ladder, which is configured in parallelrelative to the degeneration resistor. The ratio among the switches ofthe impedance letter, in various embodiments, is associated with anexponential scale.

For example, the configuration of switches is mathematically equivalentto approximating a 10^((mx+b)) function (exponential curve) with ascaled and shifted combination of

$\frac{1}{a\left( {b - x} \right)}$functions which depicts the degeneration resistance dependence. Withmore control voltages, the exponential function can be approximated withlesser error. It is to be noted that increasing the number of controllines increases the layout complexity; it may also worsen the matchingperformance since the offset voltage between them is smaller. Forvarious applications, five control signals (corresponding to fiveswitches) can be optimal in light of both performance and complexity.

To arrive at the actual ratio between the degeneration device sizes, thedetermination of switch ratio needs to factor into account that the VGAalso has to meet a minimum gain range. For example, if W₀, W₁, W₂, W₃,and W₄ are the weights of the degeneration device sizes, then at themaximum gain, the equivalent strength of all devices in parallel wouldbe:W _(total) ≈W ₀ +W ₁ +W ₂ +W ₃ +W ₄

In various embodiments, individual values of if W₀, W₁, W₂, W₃, and W₄fall along an exponential curve (with 10^(mV) ^(CTRL) ^(+b) dependence)while simultaneously adding up to a fixed W_(total) to meet the gainrange. For example, switch sizes can be determined using a system-levelmodeling/optimization tool, such as MATLAB and others. In certainembodiments, another fixed parallel resistance (e.g., such as resistorR_(DEG) or other impedance elements) to ensure a minimum gain; theinitial ratios may be tuned to accommodate for this fixed parallelresistance, as well as to compensate for any circuit non-idealities.

While the above is a full description of the specific embodiments,various modifications, alternative constructions and equivalents may beused. Therefore, the above description and illustrations should not betaken as limiting the scope of the present invention which is defined bythe appended claims.

What is claimed is:
 1. A variable gain amplifier comprising: a firstinput switch configured to receive a first differential input of thevariable gain amplifier; a second input switch configured to receive asecond differential input of the variable gain amplifier; an impedanceladder circuit comprising a plurality of switches configured with apredetermined scale for adjusting a gain of the variable gain amplifierin response to a respective plurality of control signals; and a controlcircuit to maintain a gain linearity of the variable gain amplifier, thecontrol circuit configured to (i) receive a control voltage, (ii) applya gain to the control voltage to generate a ramp voltage configured toramp each of the respective control signals upward or downward as thecontrol voltage varies, and (iii) generate the respective controlsignals for the plurality of switches based on the ramp voltage, thecontrol circuit comprising (i) a plurality of reference resistorscoupled to an output of the control circuit and configured to generatethe respective control signals based on the ramp voltage and (ii) firstand second reference current sources coupled to the plurality ofreference resistors and configured to regulate the respective controlsignals.
 2. The variable gain amplifier of claim 1 wherein thepredetermined scale is an exponential scale to configure the impedanceladder circuit to provide linear gain for an output signal of thevariable gain amplifier.
 3. The variable gain amplifier of claim 1wherein the plurality of switches comprises metal oxide semiconductorswitches.
 4. The variable gain amplifier of claim 1 further comprising abias loop coupled to the impedance ladder circuit and configured togenerate a bias current input to the impedance ladder circuit.
 5. Thevariable gain amplifier of claim 1, the control circuit comprising adigital-to-analog converter configured to convert a digital control codeto the control voltage to adjust a gain of the variable gain amplifier.6. The variable gain amplifier of claim 5, the control circuitcomprising a ramp circuit coupled between the digital-to-analogconverter and the impedance ladder circuit, the ramp circuit configuredto apply the gain to the control voltage to generate the ramp voltage.7. The variable gain amplifier of claim 6, the ramp circuit comprisingan operational transconductance amplifier configured to function as aunity gain buffer for the control voltage.
 8. The variable gainamplifier of claim 7, the operational transconductance amplifier beingconfigured in a feedback loop with the ramp voltage.
 9. The variablegain amplifier of claim 8, the operational transconductance amplifierhaving a first input coupled to the control voltage and a second inputcoupled to an output of the operational transconductance amplifier. 10.The variable gain amplifier of claim 1, wherein respective controlsignals of the plurality of control signals are output from differentpositions between the plurality of reference resistors.
 11. The variablegain amplifier of claim 10, wherein the respective control signals areoutput via taps between adjacent ones of the plurality of referenceesistors to provide different voltage values to the respective ones ofthe plurality of switches.
 12. The variable gain amplifier of claim 1,wherein each of the plurality of control signals is generated based onthe same ramp voltage.
 13. A method of operating a variable gainamplifier, the method comprising: receiving, at a first input switch, afirst differential input of the variable gain amplifier; receiving, at asecond input switch, a second differential input of the variable gainamplifier; using an impedance ladder circuit comprising a plurality ofswitches, adjusting a gain of the variable gain amplifier in response toa respective plurality of control signals; receiving a control voltage;applying a gain to the control voltage to generate a ramp voltageconfigured to ramp each of the respective control signals upward ordownward as the control voltage varies to maintain a gain linearity ofthe variable gain amplifier; generating the respective control signalsfor the plurality of switches based on the ramp voltage using aplurality of reference resistors coupled to first and second referencecurrent sources configured to regulate the respective control signals.14. The method of claim 13, further comprising using a digital-to-analogconverter to convert a digital control code to the control voltage toadjust a gain of the variable gain amplifier.
 15. The method of claim14, further comprising applying the gain to the control voltage togenerate the ramp voltage using a ramp circuit coupled between thedigital-to-analog converter and the impedance ladder circuit.
 16. Themethod of claim 15, further comprising using an operationaltransconductance amplifier as a unity gain buffer for the controlvoltage.
 17. The method of claim 16, further comprising configuring theoperational transconductance amplifier in a feedback loop with the rampvoltage.
 18. The method of claim 17, further comprising coupling a firstinput of the operational transconductance amplifier to the controlvoltage and a second input of the operational transconductance amplifierto an output of the operational transconductance amplifier.